1. Field of the Invention
The present invention relates to an insulated gate semiconductor device, and more particularly relates to an insulated gate semiconductor device which can maintain a high reverse breakdown voltage by securing a sufficient operation region area.
2. Description of the Related Art
In a conventional insulated gate semiconductor device, no transistor cell is disposed below a gate pad electrode. This technique is described for instance in Japanese Patent Application Laid-open Publication No. 2002-368218.
In addition, a protection diode having a plurality of series-connected pn junctions, for example, may be disposed below a gate pad electrode. Otherwise, a diffusion region of high-concentration impurities may also be formed in a substrate below a gate pad electrode, in order to secure a drain-source reverse breakdown voltage.
FIGS. 7A and 7B show an example of an n channel MOSFET having a p+ type impurity region provided below a gate pad electrode, as the conventional insulated gate semiconductor device.
FIG. 7A is a plan view of the MOSFET. Note that, in FIG. 7A, interlayer insulating films on a surface of a substrate is omitted, and a metal electrode layer (a source electrode 47, a gate pad electrode 48 and a gate wiring 48a) is indicated by a broken line.
Gate electrodes 43 are provided in a stripe pattern on a surface of a semiconductor substrate 31 with gate oxide films 41 interposed therebetween. The gate electrodes 43 are provided by depositing and patterning polysilicon, and a resistance thereof is reduced by introducing impurities thereinto. Source regions 45 are provided in a stripe pattern on the surface of the substrate 31 along the gate electrodes 43.
The source electrode 47 is provided on an operation region 51 in which a transistor cell is disposed, and the gate pad electrode 48 is disposed at an end of a chip. Around the chip, the gate wiring 48a connected to the gate pad electrode 48 is provided.
A gate extraction electrode 43a is provided in a pattern approximately overlapping with the gate pad electrode 48 and the gate wiring 48a. Moreover, in an n− type semiconductor layer (an n− type epitaxial layer) 31b below the gate extraction electrode 43a, a p+ type impurity region 49 is provided in a pattern approximately overlapping with the gate extraction electrode 43a. 
FIG. 7B is a cross-sectional view taken along the line e-e in FIG. 7A.
In the semiconductor substrate 31, a drain region is provided by placing the n− type semiconductor layer (the n− type epitaxial layer) 31b on an n+ type silicon semiconductor substrate 31a, and the like. On the surface of the substrate 31, a plurality of p type channel regions 34 are provided in a stripe pattern. On the surface of the substrate 31 between the channel regions 34, a plurality of the gate electrodes 43 are disposed in the stripe pattern with gate insulating films 41 interposed therebetween. On the surfaces of the channel regions 34 adjacent to the gate electrodes 43, n+ type source regions 45 are formed. The gate electrodes 43 are covered with interlayer insulating films 46, and the source electrode 47 is provided thereon, which contacts the source regions 45. A region surrounded by the gate electrodes 43 becomes one transistor cell, and a number of the transistor cells are arranged to form the operation region 51.
The gate pad electrode 48 is provided on the surface of the n− type semiconductor layer 31b outside the operation region 51, and contacts the gate extraction electrode 43a connected to the gate electrode 43 in the operation region 51. The p+ type impurity region 49 is provided in a pattern similar to that of the gate extraction electrode 43a. 
The p+ type impurity region 49 is connected to the channel region 34 and secures a source-drain reverse breakdown voltage by relieving electric field concentration at the end of the chip.
Specifically, the p+ type impurity region 49 is required to be provided in a pattern similar to that of the gate extraction electrode 43a, the pattern approximately overlapping with the gate extraction electrode 43a. Therefore, for example, in the case of the pattern in which the gate extraction electrode 43a is disposed on the entire surface below the gate pad electrode 48 as shown in FIGS. 7A and 7B, the p+ type impurity region 49 is also required to have a large area corresponding thereto.
FIGS. 8A and 8B are views for explaining the p+ type impurity region 49. FIG. 8A is a perspective view of the p+ type impurity region 49 in a circled portion shown in FIG. 7A, when seen from the operation region 51 in which the transistor cell (MOSFET) is disposed. FIG. 8B is a plan view showing another p+ type impurity region 49, with interlayer insulating films on a surface omitted, and with a metal electrode layer indicated by a broken line.
The p+ type impurity region 49 is a diffusion region and has a spherical curvature at the edge (a junction surface with the n− type epitaxial layer 31b) indicated by the circle in FIG. 7A (FIG. 8A). Here, in the pattern shown in FIGS. 7A and 7B, when a higher drain-source reverse breakdown voltage (for example, several hundred V) is required, a strong electric field is concentrated in the portion having the spherical curvature (the portion indicated by the arrows in FIG. 8A). Accordingly, there is a problem that a desired drain-source reverse breakdown voltage cannot be obtained.
Moreover, in order to reduce an on-resistance of the insulated gate semiconductor device, it is necessary to reduce a specific resistance of the n− type epitaxial layer 31b, for example. In such a case, the pattern of the p+ type impurity region 49 shown in FIGS. 7A and 7B also has a problem that the drain-source reverse breakdown voltage is deteriorated.
Specifically, when characteristics required for the operation region 51 are changed, it is necessary to change the pattern of the p+ type impurity region 49 separately from the operation region 51, in order to obtain a predetermined drain-source reverse breakdown voltage.
To be more specific, by reducing the spherical curvature, a sufficient drain-source reverse breakdown voltage can be secured. In other words, as shown in FIG. 8B, by reducing a curvature in a planar pattern of a corner portion of the p+ type impurity region 49, the spherical curvature shown in FIG. 8A can accordingly be reduced. Thus, the predetermined reverse breakdown voltage can be secured.
However, when the gate extraction electrode 43a is provided in the pattern approximately overlapping with the gate pad electrode 48 therebelow, the curvature radius of the corner portion of the p+ type impurity region 49 having the same pattern as that of the gate extraction electrode 43a is increased. Because of this, in the pattern shown in FIGS. 7A and 7B, some of the transistor cells near the gate pad electrode 48 cannot be disposed. Consequently, there is a problem that the operation region (a disposition area of the transistor cells) has to be reduced.